EtherCAT connection
The following figures show a reference circuit for connecting the NP5 EtherCAT
Note: For the standard assignment of the connections, see Pin assignment.
_1.svg)
PCI-specific pin assignment for EtherCAT:
|
Pin |
Name |
Description/function |
|---|---|---|
| A17 | SLOT_SPI_SCK |
ROM_Loaded |
| A19 | COMM_SPI_MOSI |
PDI[2] 1 |
| A20 | COMM_SPI_MISO |
PDI[3] |
| A21 | COMM_SPI_SCK |
PDI[0] |
| A22 | COMM_SPI_CS |
PDI[1] |
| A23 | I2CSCL_CANRX |
EPROM_CLK input I2 clock |
| A24 | I2CSDA_CANTX |
EPROM_DATA Input I2 data |
| 22 | COMM_RESET |
ETHERCAT_RESET |
| B23 | COMM_SYNC |
PDI[4]/SPI_IRQ |
Pin assignment NP5 ET1100 EtherCAT ASIC ET1100:
_2.svg)
Pin assignment NP5 PHY device configuration
_3.svg)
1 PDI: Process Data Interface